With the recent increase in signal transmission speed, there has been less margin for timing variation in the operating speed of an internal circuit such as a signal receiving device. For example, a flip-flop circuit (flip-flop) is required to provide the setup time and the hold time between an input clock signal and data in order to realize a normal operation. Semiconductor micro-fabrication techniques allow the speed of semiconductor devices to be increased whereas the miniaturization of circuits relatively increases their variation.
Thus, problems occur in that the setup time and the hold time of the flip-flop are reduced with an increase in the fluctuations in the data and clock timing, thus making it difficult to increase the operating speed. One method for converting digital parallel data to serial data (parallel-serial conversion) is to combine 2-bit data using a selector (or a multiplexer) to produce 1-bit data having a double data rate (see, for example, Japanese Laid-open Patent Publications No. 2000-196462, No. 8-163117, No. 2007-202033, and No. 2002-204448).
In order to shape serial data output from a selector using a flip-flop, a clock signal for the flip-flop has a timing which is, for example, delayed by half a phase with respect to the serial data. In order to perform adjustment of the timing, an existing method for adjusting the circuit delay of the clock signal using, for example, a buffer or the like has been proposed.
In the related art described above, however, a delay caused in a buffer, a selector, or the like may change depending on conditions such as process conditions, temperature conditions, or power supply conditions. Thus, a problem occurs in that it is difficult to accurately shape serial data. Furthermore, when the duty ratio of serial data output from the selector is not 50%, another problem occurs in that it is difficult to optimally adjust the timings of the clock signal and the serial data of the flip-flop.